The following nurnbers represent the sequence of word memory address accessed by the CPU in a 32-word main memory: 1,23,5, 18 ,g ,4 ,10 ,20,0,3,9, 13,6, 12,16,7.

EBB 4413 /ECB 4413 4. The following numbers represent the sequence of word memory address accessed by the CPU in a 32-word main memory: 1, 23,5,18,9,4, 10, 20, 0, 3,9,13,6, 12, 16,7 i. Assume that a direct mapped cache with a 4-line capacity with 2-word block has some initial data. Label each reference in the ist as a hit or a miss (compulsory/capacity/conflict) and show the contents of the cache in the table in APPENDIX IIl. 7 marks) Assume a 4-way set associative mapped cache with a 2- line capacity, 2-word block and LRU cache replacement method has some initial data. Assess each memory access reference in the list either as a hit or a miss and construct the final contents of the cache in the table in APPENDIX IV [8 marks] b. A processor with a 64-bit physical address space has a 2048 KB cache. A word consists of 32 bits and a cache block consists of 8 words. The cache is direct-mapped and requires 2 house- keeping bits, a valid bit and a recently used bit. Determine the total number of bytes required to implement this cache. [5 marks] 7