The following snippet of assembly includes control hazards:

BEGIN

LSR R$2,$ R$3,$ #$4$

SUB R$1,$ R$1,$ R$4$

B END

LSL R$1,$ R$4,$ #$2$

ADD R$1,$ R$2,$ R$5$

END

AND R$1,$ R$3,$ R$6$

ADD R$7,$ R$2,$ R$4$

MOV R$0,$ #$100$

B BEGIN

LDR R$9,[$R$0,$ #$0]$

LSL R$0,$ #$3$

ORR R$8,$ R$8,$ R$7$

MOV R$5,$ R$9$

a$.$ Indicate which instructions will need to be flushed for the B END and B BEGIN

instructions, and what the next instruction executed will be$.$ Assume that this code is run

on the $5-$stage processor discussed in class. Assume no forwarding, and the register file

is written to on the falling edge. Assume that there is no early branch target resolution.

Assume there is code above and below the provided code. Each part of this question is

independent from the other parts.

b$.$ Repeat part a$,$ but this time, assume we have implemented the logic to support early

branch resolution.