The following Verilog module generates a video image. Draw the image (showing screen limits and indicating colors). For what purpose are the expressions hctr-144 and vctr-33 ?

module four

(

input clk50_in,

output reg red_out,

output reg green_out,

output reg blue_out,

output reg hs_out,

output reg vs_out

);

640x480 (60 Hz) Horizontal and Vertical Synchronization (with

25 MHz Pixel Clock)

task sync (inout reg [9:0] hctr, inout reg [9:0] vctr, output reg hs, output reg vs

);

begin

if ((hctr > 0) && (hctr < 97))

96 cycle horizontal sync pulse

hs <= 0;

else

hs <= 1;

if ((vctr > 0) && (vctr < 3))

The following Verilog module generates a video image. Draw the image (showing screen limits and indicating colors). // 2 cycle vertical sync pulse

vs <= 0;

else

vs <= 1;

if (hctr==800)

begin

hctr <= 10'b0000000000; // wrap horizontal counter

if (vctr==521)

vctr <= 10'b0000000000; // wrap vertical counter

else

vctr <= vctr+1; // advance vertical counter

end

else

hctr <= hctr+1;

end

endtask

reg [18:0] count = 19'b1111111111111111111; wire clk25 = count[0];

clk_50_in / 2 reg [9:0] hctr; reg [9:0] vctr;

always @(posedge clk50_in)

count <= count + 1;

master counter

Display Digits on VGA Monitor always @(posedge clk25)

begin

if ( (480*(hctr-144) == (640*(vctr-33)))) begin

red_out = 1; green_out = 0; blue_out = 0; end

else if ( (480*(640-(hctr-144)) == (640*(vctr-33)))) begin

red_out = 0; green_out = 1; blue_out = 0; end

else begin

red_out = 0; green_out = 0; blue_out = 0; end

sync(hctr, vctr, hs_out, vs_out); end

endmodule