The fundamental of digital Logic with VHDL Design

whe PRACTICAL ASSIGNMENT Design a Meally Finite State Machine that detects when a code of 1001 or 1101 is applied to the input. The system should be continuous and after the sequence detection an LED should be switched ON. Perform the simulation to ensure that your design is working using the set of input: 01001001101001110111 a. Perform the functional simulation using Quartus and use appropriate settings b. Use the Altera board to check if your system is working correctly (choose one input w, the output LEDG and the clock at your own discretion). Double check and ensure that the selected LEDG goes ON after the code has been detected