The implementation of ANRI, a new RISC ISA, appears below. Many instructions are similar to those of MIPS, though they differ in format and other features. Like MIPS, ANRI registers are named r$0,$ r$1,...$

a$)$ How does ANRI differ from MIPS in the number of registers and the immediate size?

b$)$ Like MIPS, ANRI$$s Format R is used for three$-$register instructions such as add r$1,$ r$2,$ r$3.$ Show a possible ANRI Format R consistent with the hardware. Show the bit positions and the name of each field in ANRI Format R based on reasonable guesses. Show possible field values for add r$1,$ r$2,$ r$3$ and for or r$1,$ r$2,$ r$3.($Two instructions for a reason.$)$

c$)$ Like MIPS, ANRI$$s Format I is used for immediate instructions such as addi r$4,$ r$5,6.$ Assume that like MIPS, each of the dozens of ANRI arithmetic and logical instructions has an immediate variant. Show the bit position and name of each instruction field in ANRI Format I based on reasonable guesses and heeding the text above. Show possible field values for addi r$4,$ r$5,6$ and for ori r$4,$ r$5,6.$

d$)$ Consider load and store instructions. Show encoding of lw r$7,8($r$9)$ and sw r$10,12($r$11)$ in ANRI Format I, or something similar. Don$$t forget to base the encoding on the hardware.

e$)$ Consider procedure call instructions. Based on the implementation, why does it appear that ANRI would lack the equivalent of MIPS jal SomeProcedure though it could still encode the equivalent of jalr r$1,$ r$2.$

f$)$ Based on the hardware above, ANRI would lack a means of loading an arbitrary $32-$bit constant into a register using two instructions. Modify the hardware so that ANRI could encode an instruction like MIPS lui, one that could be used to load an arbitrary $32-$bit constant into a register using two instructions. Modify hardware to implement an instruction to help loading a $32-$bit constant. Show the format and encoding of this new instruction. The format must fit in as much as possible with existing formats.