The intel Core 2 processor has a smaller 32KB, 64-byte blocked L1 data cache, but the cache features an 8-way set associative design. The cache also uses LRU replacement policy and write- back, write -allocate based writing policy. Fill i the table for this configuration.(8 points) index hit/miss( type of miss) address Tag Px20000 K 0000 0x30000 0xi0000 px20004 x10004 0x30004 0x10004