The L1 cache of a 32-bit computer is direct-mapped, has 1024 blocks each holding 16 bytes, and includes a dirty bit. All important data paths and register unit registers in this computer are 32 bits wide. Answer Questions 7 through 14 using this given information 7. How many bytes of information from main memory can be stored in this cache? How many bits of information are stored in the cache solely to identify information within this cache? 8. How many bits of information are stored in the cache to determine if stored information is valid? 9. 10. How many bits are stored in the cache to allow lazy enforcement of Rule 1 of the Memory hierarchy? 11. As a percentage, what is the ratio of the number of other "overhead bits" that are necessary for cache function to the number of quickly-accessible bits of memory in this cache? 12. How many XOR gates are needed to construct this cache? 13. How is each bit of a 32-bit addresses used by the circuit of this cache? Address bits are named 0 through 31 going from the LSB to the MSB. 14. Give two different addresses that each map into block 17 of this cache