The logic blocks needed to implement a processors datapath have the following latencies:

I-Mem:200ps, Add: 70ps, Mux: 20ps, ALU: 90ps, Regs: 90ps, D-Mem: 250ps, Sign-Extend: 15ps, Shift-Left-2: 10ps

a. You only have one instruction: beq. What would the clock cycle time be for the single cycle implementation of this datapath?

b. You only have a lw instruction. What would the clock cycle time be for this datapath? Show your calculations.