The matrix of transistors available in a sea of gates template is shown below: IIIII All n channel transistor in the template have the minimum allowed width, while all p channel transistor have a width = times the width of n transistors to compensate for mobility ratio. a) Show the interconnect required to implement the function A.(B+C) +D using a two stage design with the above template. b) The output of A.(B+C) +D will drive a minimal inverter. Ignoring the delay due to interconnect and driver self capacitance, find the factor as a function of by which this design is slower than the same circuit implemented in custom design with transistor widths adjusted according to series parallel rules.