We had ignored the delay due to self capacitance of the driver while deriving the opti- mum conditions for a tapered inverter used for driving large capacitive loads. This led to the result that the optimum stage ratio = e for all stages. We now want to include the effect of delay due to self capacitance as a size independent addition to the stage delay. Thus, stage delay is now given by S+1/S; + p in units of 7, where 7 is the delay of a minimum inverter driving another without any self capacitance delay. a) Consider a tapered inverter with input capacitance of 1 (in units of input capac- itance of the minimum inverter) and a final load which is 1000 times the input capacitance of a minimum inverter. If we ignore the self capacitance of drivers, what is the optimum number of stages and the optimal stage ratio for this many stages? b) Derive the condition on optimum stage ratio in an inverter chain with a give number of stages when the delay of i'th stage is modeled as S+1/S; + p. What should be the product of all stage ratios? c) If we model the stage delay as Si+1/S; +2 in units of 7, with input capacitance of 1 and final load capacitance of 1000, what is the total delay of the inverter chain if we use i) 3, ii) 5, iii) 7 and iv) 9 stages to drive the final load? d) By what factor is a 3 input NAND gate and a 3 input NOR gate slower compared to the reference inverter when transistors are scaled down to offer the same input capacitance as a reference inverter? Assume the mobility ratio to be y.