The memory system of a hypothetical processor has the following parameters:

Byte addressable granularity,

30 bit physical address,

4-Way Set Associative cache,

256 K-Byte total cache capacity,

16 Bytes per cache block.

a. Show the partitioning of the physical address word. Label each field and show the number of bits in each field. Make sure that the fields are in proper sequence.

b. Replace the original Set Associative cache with a Direct Mapped cache of the same total capacity and same block size. Now how many segments are in the main memory?