The multiplexer now has a propagation delay of 10ns. Redesign the multiplexer to have a propagation delay of 3ns. du sel propagation delays for gates: 1 Number of Inputs 2 3 ins 4 Verilog Data Type Name bufifi not nand nor and Gate Tri-State Buffer Not Nand Nor And 2ns 2ns 3ns 4ns 6nsins 8ns 4ns Insons 4ns 5ns 6ns 6ns | 10ns 10ns 6ns 10ns 10ns Or or Xor Xnor xor xnor Truth table a b sel out 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 0 1