The objective of this part of the project is to design a two-stage operational amplifier. The two-stage amplifier should satisfy the following specifications: Small signal gain > 90 dB 3-dB bandwidth > 2 kHz Unity gain frequency > 85 MHz Phase margin > 60o Slew rate > 75 V/s. Power consumption < 300 w You need to design a Miller compensation capacitor and resistor to satisfy these specifications. Please use the below parameters for your design: VDD= 1.2 V CL = 2 pF Hint: You can add a common source amplifier to the folded-cascode OTA you have already designed in Part 1. Biasing: In this part of project, you can use only 1 ideal cu