The single-cycle MIPS processor below has been annotated with delays for several of the

modules (e.g., the register file has a 40ps delay). Assuming the miscellaneous, unlabeled modules have

5 ps delay, give the critical path delay for the following instructions:

7. (8 points) The single-cycle MIPS processor below has been annotated with delays for several of the modules (e.g., the register file has a 40ps delay). Assuming the miscellaneous, unlabeled modules have (5p5) delay, give the critical path delay for the following instructions: - a loud - a store - an R-Type instruction - a bey Given these critical paths, what is the maximum frequency for this datapath