The Sri version (same question, different numbers) (Based on figure 4.28):

Instruction Fetch Instruction Decode (IF) (ID) 190 130 Numbers changed for 2021 Execute (EX) 185ps Memory (MEM) 160ps Write Back (WB) 210ps A) (4.10.1)

Fill in the chart below with the name of each pipeline stage to the right of the instruction provided in the first column.

In the bottom row, write how long each pipeline stage will take in cycles.

. Assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used.

If we only have one memory (for both instructions and data), there is a structural hazard every time we need to fetch an instruction in the same cycle in which another instruction accesses data.

To guarantee forward progress, this hazard must always be resolved in favor of the instruction that accesses data.

If you need to use a spreedsheet to answer this, and paste that in (or attach it) that's ok too. 1 Time line slots 0 1 2 3 4 5 6 7 8 9 10 | 11 12 16,12(r6) r16,8(r6) r5, r4, Label ssume r5!=14 r5, r1,r4 r5,r15,r4 e in ps

The Sri version (same question, different numbers) (Based on figure 4.28): Instruction Fetch Instruction Decode (IF) (ID) 190 130 Numbers changed for 2021 Execute (EX) 185ps Memory (MEM) 160ps Write Back (WB) 210ps A) (4.10.1) Fill in the chart below with the name of each pipeline stage to the right of the instruction provided in the first column. In the bottom row, write how long each pipeline stage will take in cycles. . Assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. If we only have one memory (for both instructions and data), there is a structural hazard every time we need to fetch an instruction in the same cycle in which another instruction accesses data. To guarantee forward progress, this hazard must always be resolved in favor of the instruction that accesses data. If you need to use a spreedsheet to answer this, and paste that in (or attach it) that's ok too. 1 Time line slots 0 1 2 3 4 5 6 7 8 9 10 | 11 12 16,12(r6) r16,8(r6) r5, r4, Label ssume r5!=14 r5, r1,r4 r5,r15,r4 e in ps