The table below lists a sequence of loads and stores in the LSQ, when their one/two input operands are made available, and their computed effective addresses. Estimate when the address calculation happens for each LD/ST and when each LD/ST accesses the data memory. Assume that the processor does no memory dependence prediction to speculatively issue loads.

The register for the address calculation is made available The register that must be stored into memory is made available The calculated effective address LD/ST LD ST LD LD ST LD LD abcd abde abce abde abde abde abbe 3 8 4 7 2 6 The register for the address calculation is made available The register that must be stored into memory is made available The calculated effective address LD/ST LD ST LD LD ST LD LD abcd abde abce abde abde abde abbe 3 8 4 7 2 6