The VHDL code for two $1-$bit tristate buffers driving a $1-$bit bus is shown$\mathrm{.}1$ LIBRARY IEEE; $2$ USE ieee.std$\_$logic$\_1164.$all;$3$ ENTITY eece IS$4$ PORT$($x$,$ en : IN STD$\_$LOGIC$\_$VECTOR$(1$ DOWNTO $0)$;$5$ y : OUT STD$\_$LOGIC$)$;$6$ END;$7$ ARCHITECTURE eece$\_$arch OF eece IS$8$ BEGIN$9$ WITH en$(0)$ SELECT$10$ y $<=$ x$(0)$ WHEN $\text{'}0\text{'},11\text{'}$Z$\text{'}$ WHEN OTHERS;$1213$ WITH en$(1)$ SELECT$14$ y $<=$ x$(1)$ WHEN $\text{'}0\text{'},15\text{'}$Z$\text{'}$ WHEN OTHERS;$16$ END;Write the VHDL code that implements $2561-$bit tristate buffers driving a $1-$bit bus. To ensurethere is no syntax errors and correct operations, use the Altera tools to simulate your code.