This Assignment consists of two (2) tasks. You are required to complete both of these outside the contact hour. A detailed description of the tasks is explained below. Both of these task must be designed, simulated and implemented on Atrix A7 FPGA (Nexys) provided to you. Further, their functionalities must be verified through appropriate test strategies. Task1 Rotating and shifting Machine Introduction The aim of this task is to design a digital circuit which rotates a 4-bit input vector by a varying amount. Your design must adapt to the entity declared below. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity seven_seg_driver is port ( RotateLeft : in std_logic; en : in std_logic; N : in std_logic_vector(1 downto 0); Din : in std_logic_vector(3 downto 0); Dout : out std_logic_vector(3 downto 0) ); end seven_seg_driver; The input is applied on the port Din . The number of bits to rotate by is programmed on port N. if RotateLeft is 1, the Dout should be rotated left, otherwise right. If Enable is 0, the output on Dout should be the same as the input. Please follow the table below for further information. N Enable RotateLeft Din Dout 00 1 0 0001 0001 01 1 0 0001 1000 10 1 0 0001 0100 11 1 0 0001 0010 00 1 1 0001 0001 01 1 1 0001 0010 10 1 1 0001 0100 11 1 1 0001 1000 -- 0 - Dout=Din You are required to simulate your design using testbench. The test bench has OK signal, which should remain true. Synthesize your design to make sure the circuit does not produce any latches. The design must be critically analysed.