This exercise is intended to help you understand the relationship between forwarding, hazard detection, and ISA design. Problems in this exercise refer to the following sequences of instructions, and assume that it is executed on a 5-stagc pipelined datapath: a. ADD R5.R2.Rl LW R3,4(R5) LW R2.0(R2) OR R3,R5,R3 SW R3,0(R5) b. LWR2,0(R1) AND RI,R2,Rl LW R3,0(R2) LW Rl,0(R1) SW R1,0(R2) If there is no forwarding or hazard detection, insert NOPs to ensure correct execution. Repeat 4.21.1 but now use NOPs only when a hazard cannot be avoided by changing or rearranging these instructions. You can assume register R7 can be used to hold temporary' values in your modified code. If the processor has forwarding, but we forgot to implement the hazard detection unit, what happens when this code executes? If there is forwarding, for the first five cycles during the execution of this code, specify which signals are asserted in each cycle by hazard detection and forwarding units in Figure 4.60. If there is no forwarding, what new' inputs and output signals do we need for the hazard detection unit in Figure 4.60? Using this instruction sequence as an example, explain why each signal is needed. For the new hazard detection unit from 4.21.5, specify which output signals it asserts in each of the first five cycles during the execution of this code