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This is question 3 and the answer which is needed for this question Question: 3. Assume we have a 4-way set associative cache with 16

This is question 3 and the answer which is needed for this question

Question: 3. Assume we have a 4-way set associative cache with 16 byte blocks (Memory is byte addressable). The cache uses a Least Recently Used replacement policy and write back write policy. For simplicity, we will say the total cache size is 128 bytes. Answer the following questions about this cache. Assume each address is 8 bits total. Show work.

3.1 How long is the tag field of this cache?

3.2 How long is the index field of this cache?

3.3 How long is the block offset of this cache?

Answer:

A word consists of 4 Bytes i.e is 32 bits And each block consists of 8 bit word.

So here we have 128 bytes that will have 8*(16 bytes/word) i.e 128=27 bytes, So the offset is 7 bits.

Here it is a 4-way set so we have 2048 blocks which is 211 and for this we need 11 index bits. So the Index will be 11.

Now, the tag bit is = address bit length - exponent of index - exponent of offset

128 - 11 - 7 = 110

The tag field of the cache will be - 110

The index field of the cache is - 7

The offset block size will be - 11

4. Now, using the same cache talked about in question 3, trace through the following cache accesses by keeping track of what the cache would look like after each access. Keep track of the valid bit, dirty bit, tag in the cache. You should also label each cache access as to whether that access caused a write back to the cache. If it did cause a write back, what is the tag of the memory that was written back? Also, keep track of which cache access are cache misses and which are cache hits. In grading this, I will want to see the final state of the cache as well as whether each access was a hit, miss, and if it caused a write back. Show work.

1. LW 00110010

2. LW 01010110

3. LW 01000100

4. LW 10010011

5. LW 10110110

6. SW 00111100

7. LW 01011110

8. SW 01001000

9. LW 00001011

10. LW 00110011

11. LW 10110110

12. LW 10100110

13. LW 10111110

14. LW 11110011

15. SW 10100001

16. LW 01111100

17. LW 11010001

18. LW 00101101

19. LW 10110001

20. SW 00101001

4.1 Of these 20 accesses, what is the miss rate? What is the hit rate? (3 pts)

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