This is to be done in VHDL, you do not have to do the simulation file. I am only looking for the design file

Odd Parity A parity bit, or check bit, is a bit added to a string of binary code to ensure that the total number of 1-bits in the string is even or odd. Parity bits are used as the simplest form of error detecting code. There are two variants of parity bits: even parity bit and odd parity bit Consider the design with four inputs a,b,c,d concatenated as a string with 4 bits will do through the module to decide whether the parity bit will be 1 or 0. Following truth table describes the behavior. Design a module that maps the inputs to the switches and output to an LEDO and LED3 such that one of them turns off based on whether the parity bit needs to be O or1 0 0 0 0 Design Flow: F = a,b,c,d, +a,b,cd-a'bc'd-a'bcd'tab,c,d+ab'ed,+abc,d,+abed Reduce the expression to fewer number of literals. (Hint the design can be optimized with the use of Xor and XNor gates) Show the steps. F = a@b@c@d