This problem considers the performance of a five stage pipeline processor on a particular suite of applications. Of the instructions executed by these applications, half are ALU operations, 20% are loads, 10% are stores, 16% are conditional branches, and 4% are unconditional branches. Of the conditional branches, three-quarters are not- taken and one-quarter are taken.

1) With a perfect pipeline, a 5 stage processor would execute every instruction in 5 cycles with a CPIpp = 1. Compute the SCPI (Stall Cycles Per Instruction) on this

application suite for the following hazards: a) load-use: one of every 40 load instructions is delayed 1 cycle. b) conditional branch: every taken conditional branch is delayed 2 cycles. c) cache miss: one of every 100 memory accesses is delayed 25 cycles. d) interrupt: one of every 100,000 instructions is delayed 15,000 cycles.

2) What would be the actual CPI of a processor experiencing each of the hazards of part #1 on this application suite?

3) Use Amdahl's law to predict the speedup (on the execution of the application suite) of each of the following possible enhancements to a processor with CPIactual = 2.0.

(This processor encounters additional hazards to those listed in part #1.)

a) instruction reordering: would reduce the number of load instructions experiencing a 1 cycle load-use delay from 1 in 40 to 1 in 100

b) branch prediction: would eliminate the 2 cycle delay on one half of all taken conditional branches.

c) cache improvement: would reduce the delay associated with cache misses from 25 to 20 cycles.

4) Which of the enhancements from part #3 would provide the best improvement to the performance of the processor?