Time lel Based on the following diagram which is for a 4-bit register with 3-state outputs answer the following D The outputs (10.40) will be in high-impedance state if "P Q Do The register is triggered on the 30 on Q' CLK The input data are transferred to the flip flops when D- 30 Either Data Enable input is HIGH Either Data Inable input is Low OR O' Both Data Enable input must be HIGH Both Data Enable input must be LOW 10 Q CLA Do CR