timescale 1 ns / 1 ps module testbench; // Generate a free running 100 MHz clock // signal to mimic what is on the board. reg clk; always begin clk = l'b0; #5; clk = l'bl; #5; end // In this block, include a mechanism // to exercise the design and finally 1/ stop the simulation. reg [3:0] note; reg hush; integer loopvar; initial begin $display("If simulation ends before the testbench"); $display("completes, use the menu option to run all."); note = 4'ho; hush = l'bl; #100; $display("Beginning note loop."); // Loop through all 16 possible notes // and also exercise the hush signal. for (loopvar = 0; loopvar