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To reduce branch delay, assume we move the 6 followings to ID stage: Target address adder and Register comparator. Also, assume we use forwarding when

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To reduce branch delay, assume we move the 6 followings to ID stage: Target address adder" and "Register comparator". Also, assume we use forwarding when possible. How many stall cycles are needed if a comparison register is a destination of immediately preceding load * instruction 1 (1 ) stall 1 O stalls 2 O no stalls o stalls 3 None of the stated answers O

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