(Total 15 Marks) 2. A B O E Boo i. Figure 2.1 Behavioral modeling and Structural modeling are two well-known modeling styles in HDL design. Explain them in brief and provide suitable application scenarios. (06 marks) Consider the logic circuit given in Figure 2.1 a. Write the Verilog code for the above design (03 marks) ii. 5 b. What is the modelling approach that you followed in 2. ii. a. ? Justify your selection. (04 marks) iii. Instantiation is the process of creating objects from a module template, and the objects are called instances. Each instance is a complete, independent and concurrently active copy of a module. A module can be instantiated in another module thus creating hierarchy. Every instance are connected to the main module through port mapping. a) What are the two types of port mapping available in Verilog? (02 marks) b) You have to instantiate a module which has several inputs and outputs. Also, It should be instantiated several times within the main module. Given this scenario, what type of port map you would choose? Justify your selection. (05 Marks) (Total 20 Marks)