Traffic light

verilog and modelsim

1. The green light maintains 1024 cycles. (Starting state) 2. There is no light signal to maintain 128 cycles. 3. The green light maintains 128 cycles. 4. There is no light signal to maintain 128 cycles. 5. The green light maintains 128 cycles. 6. Switch to yellow light to maintain 512 cycles. 7. Switch to red light to maintain 1024 cycles Input signal: (The circuit is triggered by clock positive edge pass: 1bit signal. When pass is 1, if the current state is not the green light of the initial state, it is forced to switch to the first cycle of the green light of the initial state. If it is the green light of the initial state, the light and cycle will not be changed. When pass is 0, there is no action. rst: 1bit signal, triggered when non-synchronous positive edge, set the light status to the first cycle of the green light. clk: 1bit clock signal. Output signal: R: 1bit signal, representing the output signal of the red light. G: 1bit signal, representing the output signal of the green light. Y: 1bit signal, representing the output signal of the yellow light. 1. Complete the design of traffic_light.v. 2. Using the steps in modelsim teaching, put traffic_light.v and traffic_light_tb.v into modelsim project to perform simulation

Green (1024 cycles) None (128 cycles) Green (128 cycles) Red (1024 cycles) 1 None (128 cycles) Yellow (512 cycles) Green (128 cycles) Figure 2. pass R rst traffic_light clk Figure 3. Green (1024 cycles) None (128 cycles) Green (128 cycles) Red (1024 cycles) 1 None (128 cycles) Yellow (512 cycles) Green (128 cycles) Figure 2. pass R rst traffic_light clk Figure 3