True False 6 module Simple_Circuit (A,B,C,D); output D; input A,B,C; wire w1,w2,W3,W4; not G3 (w2,wl); and G1 (w1, A,B); G2 (w3,B,C); not G4 (W4,W3); or G5 (D,W2,W4); endmodule or Considering the following Verilog module, draw a corresponding logic diagram. (Anonim olmayan soru ) ) (15 Puan)