Trur or false?

Temporal locality refers to the idea that data in memory which is close in address to memory data that has recently been accessed is likely to be accessed soon.

Increasing the block size of cache memory is likely to improve performance primarily because programs exhibit spatial locality.

For a virtual memory system with $48-$bit physical addresses, a single page table, and $8KB$ physical page size, the width $($i$.$e$.$ the number of bits$)$ of the physical page number portion of an address is $30$ bits.

A CPU with a faster clock frequency always has higher performance than one with a slower clock.

A pipelined datapath must have separate instruction and data memories because the format of instructions is different from the format of data.