UD='0' UD='1' State6 Out="1000" The following state diagram in Fig. 3 is a finite state machine (FSM) showing seven outputs of 4-bit width. When enable (CE) is '0', it remains at current state. When Reset is '1' at any state, it outputs "000" else it outputs the next state. Develop the complete VHDL Code describing the FSM design shown in Fig. 3 include its Entity and Architecture. CE='0' UD='0' CE='0' UD='0' State0 Out-"0000" State1 UD='0' Out-"1010" State 7 UD='1' UD='1' Out "0001 UD='1' CE='0' UD='0' UD='1' CE='0' Reset = '1' UD='1' State5 UD='1' UD='1' Out "0111" UD='0' State4 Out-"1011" UD='0 State3 Out-"0100" CE='0' CE='0' UD='0' State2 Out = "0011"