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3. Design a VHDL model to implement the behavior described by in Fig. 3. Use concurrent signal assignments and minimized logical operators. Declare your entity to match the block diagram provided. Use the type bit for your ports. Note: 'X' means don't care. (4 marks) Systemc 17 F C D FO F1 0 0 0 0 1 0 1 1 0 0 1 0 0 1 1 0 0 0 0 X 1 1 0 0 B|0|0|00|1|1|1|1|0|000 1 1 0 1 0 0 0 1 1 1 0 0 0 0 1 1 1 Oo oo 0 1 0 1 1 0 X X 1 1 1 0 0 0 1 1 1 1 0 1 1 1 0 1 X X X 1 1 FO= EA,B,C,D(1,5,6, 11, 12, 13, 14), F1 = A,B,C,D(6, 7, 8, 9). Fig 3. System functionality