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According to the above schematic, the 2-to-1 multiplexer outputs the input signal A when the selector signal S is equal to 0 otherwise it outputs the input signal B. In this lab, you will implement this 2-to-1 multiplexer in VHDL using structural and behavioral styles. In the structural modeling of the 2-to-1 multiplexer in VHDL, the multiplexer is implemented using AND, OR or NOT gates only. More specifically, the structural description of the multiplexer literally realizes its boolean function. Describe the boolean function in VHDL using AND, OR or NOT gates only. Use the following entity declaration for your VHDL description of the 2-to-1 multiplexer: library IEEE; use IEEE.STD_LOGIC_1164. ALL; use IEEE . NUMERIC_STD. ALL; entity MUX_structural is Port (A : in std_logic; : in std_logic; S : in std_logic; Y : out std_logic); end MUX_structural; Once completed, you will describe the architecture of the 2-to-1 multiplexer using behavioral style. In the behavioral description, you describe the behavior of your target circuit and the synthesis tool creates a gate-level layout of your de- sign. Use a single VHDL select assignment only and the entity declaration below to implement a behavioral description of the 2-to-1 multiplexer (see the previous VHDL assignment for more details). library IEEE; use IEEE.STD_LOGIC_1164. ALL; use IEEE . NUMERIC_STD. ALL; entity MUX_behavioral is Port (A : in std_logic; B std_logic; std_logic; : out std_logic); end MUX_behavioral; s Y : in : in Once described both behavioral and structural styles of the 2-to-1 multiplexer in VHDL, you are required to test your circuits. Write a testbench code and perform an exhaustive test for your VHDL descriptions of the 2-to-1 multiplexer