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Consider a virtual memory system using a 4-level page table where the parameters n and p are 48 and 12, respectively. The size of the DRAM i5 4GB. The number of bits of virtual address used for indexing into the first-, the second-, and third-level page tables are 8, 8, and 10, respectively. Suppose each page table entry in the outermost level is 8 bytes long. How much memory is required for the page tables translating the user portion of the address space when the process address space looks as follows: The code+data segment grows upwards starting from address Ox000000000000 and is of size 4 MB. The heap grows upwards from address OxOOODOO000000 and is of size 12 MB. The stack grows downwards from address 0xc00000000000 and is of size 1 MB