Use Pareto analysis to investigate the data collected on a printed-circuit-board assembly line. Click the icon to view the data. a) Based on the data, choose the correct graph below. O A. O C. Number of defects Number of defects 600- 400- 200- 600- 400- 200- G C CAD F F B BE CGDF A B E b) The Pareto chart indicates that most of the errors, %, are the result of excess adhesive O B. circuitry problems on final test wrong component O D. components not adhering misplaced transistors defective board dimension Number of defects Number of defects 600- 400- 200- 0- 600- 400- 200- mounting holes improperly positioned 0- G C D A B F GCD AF BE (round your response to one decimal place).