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Use SystemVerilog to design a module that performs one of four operations on two 4-bit inputs to produce one 4-bit output as specified below. Use
- Use SystemVerilog to design a module that performs one of four operations on two 4-bit inputs to produce one 4-bit output as specified below. Use alwaysand case statements, and begin endstatements if needed. Include explanatory comments in the modules SystemVerilog code as needed.
- Write a SystemVerilog testbench
- Use loop statement(s) to provide enough tests of all possible input combinations.
- After assigning the loop variable(s) to drive the stimulus to your device under test, insert a #10 to advance simulation time before checking the results.
- Use a casestatement to provide a different assert statement for each of the four functions. Display error messages for failures.
Problem: 1. Use SxstemVerilog to design a module that performs one of four operations on two 4-bit inputs to produce one 4-bit output as specified below. Use always and case statements, and begin - end statements if needed. Include explanatory comments in the module's Systemerilag code as needed. Inputs Outputs y3:0] al3:0], b[3:0], s[1:0] s function o y-a +b, unsigned add 1y a
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