Use the following information related to the five stages of our MIPS datapath:

Instruction Fetch takes 400ps.

Instruction Decode takes 200ps.

Execute stage takes 200ps

Memory Stage (i.e., read and write data memory) takes 200ps

Write Back (i.e., writing a result in a register) takes 100ps.

a. For a single cycle design, what is the minimum clock cycle time for proper execution?

b. How much time does it take to implement the following code segment on the single cycle design?

lw $1, 100($0)

lw $2 200($0)

lw $3, 300($0)

lw $4, 400($0)

c. For a 5-stage pipeline, what is the minimum clock cycle time for proper execution?

d. How much time does it take to implement the above code segment on the pipelined design?