Use the following table to answer questions 1-3. Assume the individual stages of the MIPS datapath have the following latencies: WB 180 ps MEM ID 300 ps EX 150 ps IF 320ps 200 ps 1. What is the clock cycle time in a pipelined processor? 2. What is the clock cycle time in a non-pipelined processor? 3. What is the total latency of sw instruction in non-pipelined processor