Use the least number of full adders to design a multiplier that multiplies a $3-$bit unsigned binary number X$2$ X$1$ X$0$ by a $2-$bit unsigned binary number Y$1$ Y$0($using an array of full$-$adder cells.$)$ Determine the worst case propagation delay if each full adder takes $10ns$ to produce its $C$ and $S$ outputs, and each AND gate $($used to generate the product components$)$ has $5ns$ of propagation delay.