Use VHDL to build a structural counter. The state of the counter should be incremented only once for each clock cycle if the enable input is asserted (1). You will also need to include a synchronous reset mechanism that initializes the counter to the input value when the reset input is asserted (1). The value of the enable input does not matter if the reset is asserted. When the reset input is deasserted (0) the counter should increment with each clock cycle when the enable is asserted. If neither the reset nor the enable is asserted, then the counter state does not change. Here is the entity declaration for counter:

ENTITY Counter IS GENERIC (width : NATURAL RANGE 1 TO 64 := 8); PORT ( D : IN std_ulogic-vectr (width- 1 DOWNTO 0); oOUT std ulogic_vector (width - 1 DOWNTO O) Clock, enable, reset : IN std ulogic) END ENTITY Counter ENTITY Counter IS GENERIC (width : NATURAL RANGE 1 TO 64 := 8); PORT ( D : IN std_ulogic-vectr (width- 1 DOWNTO 0); oOUT std ulogic_vector (width - 1 DOWNTO O) Clock, enable, reset : IN std ulogic) END ENTITY Counter