Using the ALU below

module alu(inp1, inp2, sel, out); input[3:0] inp1, inp2, sel; output[3:0] out; reg[3:0] out;

always @(inp1, inp2, sel) begin case(sel) 4'b0000: begin out = inp1 + inp2; end // Addition 4'b0001: begin out = inp1 - inp2; end // Subtraction 4'b0010: begin out = inp1 - 1; end // Subtract by 1 4'b0011: begin out = inp1 + 1; end // Add by 1 4'b0100: begin out = inp1 & inp2; end // Logical AND 4'b0101: begin out = inp1 | inp2; end // Logical OR 4'b0110: begin out = ~ inp1; end // LOGICAL NOT 4'b0111: begin out = (inp1 ^ inp2); end // XOR 4'b1000: begin out = inp1 << 4'b0010; end // Logical shift Left 4'b1001: begin out = inp2 >> 4'b0011; end // Logical shift Right default: begin out = 4'b0000; end // This line is very important endcase end endmodule

• Modify the ALU generate a sum and a carry.

• Modify the ALU to add an input carry and generate a sum and a carry

• Modify the ALU to implement subtraction using twos complement

• Modify the ALU to compare two 4-bit inputs