USING VERILOG PLEASE

Objectives: To design and construct a synthesizable Finite State Machine and Datapath which computes the greatest common denominator (GCD) of two numbers as explained & discussed in lecture.

Problem: Implement one of the two GCD FSMD designs discussed in the class lecture and outlined in the slide set. Those two designs are your only options. DescriptionYour design will take in two 4-bit numbers and output the binary value of the greatest common divisor of those two numbers. The numbers will be input via the dip switches, the result will be output via the LEDs, and control is done via pushbuttons.

Your design will consist of two components - the controller and the datapath. The controller is to be a pure FSM. The datapath operates based on signals generated by the controller FSM - it should have no independent controlling logic.

IMPORTANT: The datapath must be constructed structurally. This means that you can only instantiate components, and connect them with wires. You will need to create individual components (Adder, Comparator, Register, etc) for each element in the datapath. Registers are the only clocked component, and they should be triggered by the clock on the opposite edge than that of the Controller FSM. All non-register components must be purely combinational - no sequential elements. Your registers should have some type of enable signal for control, and a separate reset signal. Check the Template library for examples/starting points.