Using Verilog to implement single-cycle MIPS ISA-based processor. The processor should support R type and I type instructions. Testbench Design: The testbench should be designed in a way that fully tests the function of processor Materials to be submitted: 1. Verilog codes for modules 2. Verilog codes for testbenchs 3. Image of the screen that shows the test results. 4. Waveforms