V. (24 points=15+9) Consider the following state transition diagram representing the behavior of a sequential logic. Assume that the state of the circuit is represented by QAQ (use two D-FFs and the state assignment 00:50, 01: S1, 10:52. & 11:53). Note that X is the input and Z is the output. 2x=0/2= 2==0 x=1/2=1 Spe Xx=1lz=0 x=dlz=1 (52 Ix=1lz=0 ) Ox=olz=1 53. x= zo (a) Fill in the next state and output columns of the state transition table. PS Input NS QA Q3 X QA Q3 Output FF Controls Z DA DE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 6) Implement the next state & output logic using a 3:8 Decoder and OR gates