Verilog Counter from 0 to 3: Here is most of the code, just need the codermod code which I'm not sure how to go about: module TestMod; reg CLK; wire Q0, Q1, Q2, Q3, C1, C0; always begin // this is clock wave CLK = 0; // 0 for half cycle (#1) #1; CLk = 1; // 1 for half cycle (#1) #1; end RippleMod my_ripple(... arguments ...) CoderMod my_coder(... arguments ...) initial #16 $finish; initial begin $display("... header ..."); $monitor("... items ...", ...); end endmodule module CoderMod(4 unary input and 2 binary output); input are these output are these logic gate statement to define an output from input logic gate statement to define an output from input endmodule module RippleMod(CLK, Q0, Q1, Q2, Q3); input CLK; output Q0, Q1, Q2, Q3; reg Q0, Q1, Q2, Q3; always @(posedge CLK) begin Q0   The use of memory constitutes a sequential-logic circuit. The memory in Verilog programming is the use of reg to declare bit storage which can contain a state of the electronics, and can be used as part of the input to generate the next state in time driven by clock cycles. Simple examples of sequential circuits are counters This assignment we will code a Verilog programs for simulation of a Ripple Counter which is one of various types of counters The way a ripple counter is constructed: a single value 1 is being passed among several bit registers, and the collective output of these registers will thus form a unary pattern. This pattern is then given to an encoder, and the output of the encoder will be binary. That is said to be a binary two-bit counter: 1000->002, 0100->01,, 0010->102, 0001->112, and repeat. Ripple Counter Unary t0 Binary Ripple CLK Ripple Sequence Generator CLK Suppose the output of the 4 registers above are Q0, Q1, Q2, and Q3. Then, the truth table for encoding 00 q1 Q2 Q3 Ci C 1 0 0 e e Therefore, C1 is 1 when either Q2 or Q3 is 1; otherwise 0. 0 1 0 1 And, CO is 1 when either Q1 or Q3 is 1; otherwise0 0 1 0 1 This defines how the encoder module processes internally 0 0 0 1 1 1 Your goal is to program a counter that counts from 0 to 3 and repeat See the given example code to program the clock signal generation correctly. In the ripple counter, all counting registers are initiallv set zero except the first one is 1 so to pass it to the next register upon a new clock cycle. Your Verilog programs should generate the same output as how the demo runs Output of counter: count from 0 to 3. Time CLK Q 0 1000 00 1 1 0100 01 2 0100 01 3 1 0010 10 4 0010 10 5 1 0001 11 6 0 0001 11 7 1 1000 00 8 0 1000 00 9 1 0100 01 10 0100 01 11 1 0010 10 12 0010 10 13 1 0001 11 14 0001 11 15 1 1000 00 16 0 1000 00