Verilog File. My teacher never taught us the syntax of Verilog. Could you please tell me what errors I am making. This is an encoder/ decoder program. The encoder will have an 8-bit input (In7:In0) with 3 outputs (Out2:Out0)

Encoder_tb.v

Decoder.v

EncDec_tb.v

1 timescale 1ns / 1ps 2 module Encoder (In, Out, Good) 4 input 7:O] In; 5 output [2:0] Out; Good 6 output 7 [2:01 Out; Good 8 reg 9 wire 10 11 assign 12 13 alwayse) 14 15 16 17 18 19 20 21 begin case (In) 8,b0000 0001: 8,b0000 0010: 8,b0000 0100: 8,b0000 1000: 8,b0001 0000: 8,b0010 0000: 8.b0 100 0000: 8"b1000 0000: endcase Out Out Out Out Out Out Out Out 3'b000; 3'b001; 3'b0 10; 3'b0 1 1 ; 3"b100; 3"b101; 3"b110; 3 'b111; 23 2 4 25 2 6 27 endmodule = end 29 timescale 1ns / 1ps 30 module Encoder tb; 31 32 reg [7:0] EncIn; 33 wire [2:0] Encout; 34 integer 35 36 Encoder dut ( 37 . In (EncIn), .Out (EncOut) 39 41 initial begin Enc1n= 8 'b0000 for (i=0 ; 1