VERILOG FSM: Sequence 00,01,11,10 Example A complete FSM is constructed by combining the VERILOG next state function and D flip-flops. This exercise provides the VERILOG next_pattern, the dff module, and the fsm module. Only the next_pattern has to be completec. Complete the VERILOG next_pattern module, that provides the next state table for a sequence generator The sequence is 00, 01,11, and 10. The reset state is 00. The dff module provides a positive edge trigger D flip-flop with a specified reset state give by the init parameter The fsm module connects next_pattern and dff modules together. You should copy the bodies of these modules for the following sequence generator exercises (some modification might be required). /l pos edge d flip-flop with init module dff #(parameter N-4, init-01 output logic [N-1:0] q, input logic [N-1:0] d, input logic clk, reset) always-ff @iposedge clk) q