verilog hdl

please as soon as possible

(9 points) Assuming that someone has prepared a Verilog design of a 4 bit universal shift register. Show how you can test his/her design and verify that it is functional. the module is declared as follows: module Shift_Reg output reg [3:0] A_par, input [3:0] par, input 51, 50, MSB_in, LSB_in, CLK, Clear_b); A_par 50 MSB_in Shift_Register LSR_in CLK Clear _par Mode Control S1 so 0 0 0 1 1 1 1 Register Operation No change Shift right Shift left Parallel load 0