verilog please one file

Operation 2: Using the concept of Full-Adder, perform the following addition: Output =( Odd value of X)+( Even Value of Y) Note: the circuit should allow 0 as even value for Y. Where X&Y are 3-bits binary inputs such as: X takes the lest 3 bits from the input ([[2],I[1],I[0]), such as X[2..0] will be as the following: - X[2]=l[2] - X[1]=[1] - X[0]=I[0] Y takes the most 3 bits from the input (I[5],I[4],I[3]), such as Y[2..0] will be as the following: - Y[2]=[5] - Y[1]=[4] - Y[0]=I[3] Design the problem in Quartus as block diagram schematic or Verilog then verify using waveform. Note: All Operations must be Block Symbols to be combined as final Design file (Block diagram)