!!!!!VERILOG QUESTION!!!!! Verilog HDL was invented by Phil Moorby and Prabhu Goel around 1984. It served as a proprietary hardware modeling language owned by Gateway Design Automation Inc. At that time, the language was not standardized. It modified itself in almost all the revisions that came out between 1984 to 1990. In 1990, Gateway Design Automation Inc was acquired by Cadence Design System, which is now one of the biggest suppliers of electronic design technologies and engineering services in the electronic design automation (EDA) industry. Cadence recognized the value of Verilog, and realized that if Verilog remained as a closed language, the pressure of standardization would eventually drive people to shift to VHDL. So in 1991 the Open Verilog International (OVI) (now known as Accellera) was organized by Candence and the documentation of Verilog was transferred to public domain under the name of OVI. It was later submitted to IEEE and became IEEE standard 1364-1995, commonly referred as Verilog-95. In 2001, extensions to Verilog-95 were submitted back to IEEE and became IEEE standard 1364-2001, known as Verilog-2001. The extensions covered some deficiencies that users had found in the Verilog-95. One of the most significant upgrades was that signed variables (in 2.s complement) became supported. Verilog-2001 is now the dominant edition of Verilog supported by most design tools. In 2005, Verilog-2005 (IEEE Standard 1364-2005) was published with minor corrections and modifications. Also in 2005 System Verilog, a superset of Verilog-2005, with many new features and capabilities to aid design verification, was published. As of 2009, System Verilog and Verilog language standards were merged into System Verilog 2009 (IEEE Standard 1800-2009), which is one of the most popular languages for IC design and verification today. Xilinx Vivado Design Suite, released in 2013, can support System Verilog for FPGA design and verification. Using the code example below, construct in verilog hdl a variable cycle ring counter that covers a max of 18 T states 1 Produle mRingCounter ( input icik, //CLK input iReset, //CLR output 05:01 Ringt cantar, output 15:0] Ring Counter //lhas 3 1 IlipFlop JK NeyEdy Cik Posest gbus Ringcounter 01. J{Ring CounterDar 1511, ikoRinyCounter [5]). .ilk-C1x), iReselliReset), .QloRingCountert01), .2bar (RingCounter Bar[0])); FlipFlop_JK_NeyEdgeclk_Posket_chal RingCounter_11.JokinyCounter Barlo!, ikioning Counter[O]), .iCLK CLK), .iReset Likeset), .00(orioy Counter [1]], .bar CoRingcounterBar[1])}; lipriop_JK_Neglidgelk Pakat Ubar Ringcounter 21.1J (okingCountertill. .ik (okingcounter Har:1). .iclk iclk). .. Reacti Reset). ..(okingCounter1211. cobarokingcounterBar217; 10 FlipFlop JK Negligecik Posts Our Rice Counter 31.1J (Ringuunter [211, ikoRingCounterBar[2]), .ilk.clx), iResel(iRese), Qloring Counter [3]), obar (oring CourlerBar [3])); 11 FlipFlop_JK_NeyEdgecik_Poskat_gla RidgCounter_41. JokinyCounter [3]], ikioningcounterBar [3]). .iCLK CLK), ileset liReset), .(ofinyCounter [4]), .ar (Ring Counter Bac[4])): 12 P'lipFlop JK Neglidget:lk Poskat Obar Ringcounter 51.1 Jaringcounter 1411, .i Kloringcounterkar[41), .iclkicik), .i Resot lienet). ..(okingcounter 51. cobar lokingcounterkar 51) 13 14 encodule !!!!!VERILOG QUESTION!!!!! Verilog HDL was invented by Phil Moorby and Prabhu Goel around 1984. It served as a proprietary hardware modeling language owned by Gateway Design Automation Inc. At that time, the language was not standardized. It modified itself in almost all the revisions that came out between 1984 to 1990. In 1990, Gateway Design Automation Inc was acquired by Cadence Design System, which is now one of the biggest suppliers of electronic design technologies and engineering services in the electronic design automation (EDA) industry. Cadence recognized the value of Verilog, and realized that if Verilog remained as a closed language, the pressure of standardization would eventually drive people to shift to VHDL. So in 1991 the Open Verilog International (OVI) (now known as Accellera) was organized by Candence and the documentation of Verilog was transferred to public domain under the name of OVI. It was later submitted to IEEE and became IEEE standard 1364-1995, commonly referred as Verilog-95. In 2001, extensions to Verilog-95 were submitted back to IEEE and became IEEE standard 1364-2001, known as Verilog-2001. The extensions covered some deficiencies that users had found in the Verilog-95. One of the most significant upgrades was that signed variables (in 2.s complement) became supported. Verilog-2001 is now the dominant edition of Verilog supported by most design tools. In 2005, Verilog-2005 (IEEE Standard 1364-2005) was published with minor corrections and modifications. Also in 2005 System Verilog, a superset of Verilog-2005, with many new features and capabilities to aid design verification, was published. As of 2009, System Verilog and Verilog language standards were merged into System Verilog 2009 (IEEE Standard 1800-2009), which is one of the most popular languages for IC design and verification today. Xilinx Vivado Design Suite, released in 2013, can support System Verilog for FPGA design and verification. Using the code example below, construct in verilog hdl a variable cycle ring counter that covers a max of 18 T states 1 Produle mRingCounter ( input icik, //CLK input iReset, //CLR output 05:01 Ringt cantar, output 15:0] Ring Counter //lhas 3 1 IlipFlop JK NeyEdy Cik Posest gbus Ringcounter 01. J{Ring CounterDar 1511, ikoRinyCounter [5]). .ilk-C1x), iReselliReset), .QloRingCountert01), .2bar (RingCounter Bar[0])); FlipFlop_JK_NeyEdgeclk_Posket_chal RingCounter_11.JokinyCounter Barlo!, ikioning Counter[O]), .iCLK CLK), .iReset Likeset), .00(orioy Counter [1]], .bar CoRingcounterBar[1])}; lipriop_JK_Neglidgelk Pakat Ubar Ringcounter 21.1J (okingCountertill. .ik (okingcounter Har:1). .iclk iclk). .. Reacti Reset). ..(okingCounter1211. cobarokingcounterBar217; 10 FlipFlop JK Negligecik Posts Our Rice Counter 31.1J (Ringuunter [211, ikoRingCounterBar[2]), .ilk.clx), iResel(iRese), Qloring Counter [3]), obar (oring CourlerBar [3])); 11 FlipFlop_JK_NeyEdgecik_Poskat_gla RidgCounter_41. JokinyCounter [3]], ikioningcounterBar [3]). .iCLK CLK), ileset liReset), .(ofinyCounter [4]), .ar (Ring Counter Bac[4])): 12 P'lipFlop JK Neglidget:lk Poskat Obar Ringcounter 51.1 Jaringcounter 1411, .i Kloringcounterkar[41), .iclkicik), .i Resot lienet). ..(okingcounter 51. cobar lokingcounterkar 51) 13 14 encodule