Verilog uses more than one type of assignment operator. There are two operators used. The first is $\text{'}=\text{'},$ and the second is Each operator has a different semantic behaviour when used inside an initial or always block.

What is the difference between the two operators $(2$ Marks$),$ and under what circumstances should you use the operator? $(2$ Marks$)$

In your answer explain the difference between blocking and non$-$blocking assignments.